Robert Bedichek, ``Some Efficient Architecture Simulation Techniques
Proceedings of the USENIX Winter 1990 Technical Conference, 1990.

Abstract: An efficient simulator for the Motorola 88000 at the ISA
(Instruction Set Architecture) level is described. By translating
instructions on the fly to a quick-to-execute form we achieve an
average ratio of 20 simulator host instructions executed per simulated
instruction. Lazy allocation of memory allows large memories to be
modelled with low start-up time. We describe our experience using the
simulator to develop workstation software. The simulator's speed and
extensive I/O device modelling make it possible for us to
interactively debug and test a UNIX(r) kernel and diagnostic software
well before the hardware was available.  Extensions to closely model
caches and multiprocessors are sketched.