THIS CATEGORY NOT YET ORGANIZED.
Generally, the closer the match between the
the easier it is to write a simulator,
and the better the efficiency.
Possible mismatches include:
Note that target support for self-modifying code may be treated as a
special case of synchronization.
For example, target machines with no caches or unified instruction and
data caches will typically write instructions using ordinary store
Therefore, all store instructions must be treated as potential
- Byte or word size.
simulates a machine with 36-bit words;
it runs on machines with 32-bit and 64-bit words.
- Numeric representation.
For example, whether integers are sign-magnitude,
one's complement, or two's complement.
Or, for example,
which simulates all VAX floating-point formats
on a host machine that lacks some of the VAX formats.
- Which instruction combinations cause exceptions,
and how those exceptions are reported.
- Synchronization and atomicity.
In particular, the details may be messy
where the target machine synchronizes
implicitly and the host does so explicitly,
since all target operations that might
cause synchronization generally need to be treated as if they
For timing-accurate simulation
some matches between the host and target can improve the efficiency,
but many do not.
From instruction-set simulation and tracing